Along with the means of arithmetic calculations, the microprocessor instruction system also has means of logical data conversion. By logical we mean such data transformations, which are based on rules of formal logic.

Formal logic works at the level of true and false statements. For a microprocessor, this usually means 1 and 0, respectively. The computer is native to the language of zeros and ones, but the smallest unit of data that machine instructions operate on is the byte. However, at the system level, it is often necessary to be able to operate at an extremely low level—the bit level.

Rice. 29. Logical data processing tools

The means of logical data transformation include logical commands and logical operations. The operand of an assembler instruction can generally be an expression, which in turn is a combination of operators and operands. Among these operators there may also be operators that implement logical operations on expression objects.

Before examining these tools in detail, let’s consider what the logical data itself is and what operations are performed on it.

Logical data

The theoretical basis for logical data processing is formal logic. There are several systems of logic. One of the most famous is propositional calculus. A statement is any statement that can be said to either true, or false.

Propositional calculus is a set of rules used to determine the truth or falsity of some combination of statements.

Propositional calculus is very harmoniously combined with the principles of computer operation and the basic methods of programming it. All computer hardware components are built on logic chips. The system for representing information in a computer at the lowest level is based on the concept of a bit. A bit, having only two states (0 (false) and 1 (true)), fits naturally into propositional calculus.

According to the theory, the following logical operations can be performed on statements (on bits).

1. Negation (logical NOT) - a logical operation on one operand whose result is the inverse of the original operand.

This operation is uniquely characterized by the following truth table (Table 12).

Table 12. Truth table for logical negation

2. Logical addition (logical inclusive OR) - a logical operation on two operands whose result is true (1) if one or both operands are true (1), and false (0) if both operands are false (0).

This operation is described using the following truth table (Table 13).

Table 13. Truth table for logical inclusive OR

3. Logical multiplication (logical AND) - a logical operation on two operands that evaluates to true (1) only if both operands evaluate to true (1). In all other cases, the value of the operation is false (0).

This operation is described using the following truth table (Table 14).

Table 14. Truth table for logical AND

4. Logical exclusive addition (logical exclusive OR) - a logical operation on two operands whose result is true (1) if only one of the two operands is true (1), and false (0) if both operands are false (0) or " truth" (1). This operation is described using the following truth table (Table 15).

Table 15. Truth table for logical exclusive OR

The microprocessor instruction system contains five instructions that support these operations. These instructions perform logical operations on the bits of the operands. The dimensions of the operands, naturally, must be the same. For example, if the size of the operands is a word (16 bits), then the logical operation is performed first on the zero bits of the operands, and its result is written in place of bit 0 of the result. Then the command sequentially repeats these actions on all bits from the first to the fifteenth.

Logical commands

The microprocessor instruction system has the following set of commands that support working with logical data:

1) and operand_1, operand_2 – logical multiplication operation. The command performs a bitwise logical AND operation (conjunction) on the bits of the operands operand_1 and operand_2. The result is written to operand_1;

2) og operand_1, operand_2 – logical addition operation. The command performs a bitwise logical OR operation (disjunction) on the bits of the operands operand_1 and operand_2. The result is written to operand_1;

3) hog operand_1, operand_2 – logical exclusive addition operation. The instruction performs a bitwise logical exclusive OR operation on the bits of the operands operand_1 and operand_2. The result is written in place of the operand;

4) test operand_1, operand_2 – “check” operation (using logical multiplication). The command performs a bitwise logical AND operation on the bits of the operands operand_1 and operand_2. The state of the operands remains the same, only the flags zf, sf, and pf change, which makes it possible to analyze the state of individual bits of the operand without changing their state;

5) not operand – logical negation operation. The command performs a bitwise inversion (replacing the value with the opposite one) of each bit of the operand. The result is written in place of the operand.

To understand the role of logical instructions in the microprocessor instruction system, it is very important to understand the scope of their application and typical techniques for using them in programming.

Using logical commands it is possible allocation individual bits in the operand for the purpose of setting, resetting, inverting or simply checking for a certain value.

To organize such work with bits, operand_2 usually plays the role of a mask. Using the bits set in 1 bit of this mask, the operand_1 bits needed for a specific operation are determined. Let us show what logical commands can be used for this purpose:

1) to set certain bits to 1, use the command og operand_1, operand_2.

In this instruction, operand_2, which acts as a mask, must contain one bits in place of those bits that should be set to 1 in operand_1;

2) to reset certain bits to 0, use the command and operand_1, operand_2.

In this instruction, operand_2, which acts as a mask, must contain zero bits in place of those bits that should be set to 0 in operand_1;

3) command hog operand_1, operand_2 is applied:

a) to find out which bits in operand_1 and operand are different;

b) to invert the state of the specified bits in operand_1.

When executing the hog command, the bits of the mask that interest us (operand_2) must be one, the rest must be zero;

To check the status of the specified bits, use the command test operand_1, operand_2 (check operand_1).

The checked bits of operand_1 in the mask (operand_2) must have a value of one. The operation of the test command is similar to the algorithm of the and command, but it does not change the value of operand_1. The result of the command is to set the value of the zero flag zf:

1) if zf = 0, then the logical multiplication resulted in a zero result, i.e. one unit bit of the mask, which did not match the corresponding one bit of the operand;

2) if zf = 1, then the logical multiplication resulted in a non-zero result, i.e. at least one the one bit of the mask matches the corresponding one bit of operand_1.

To react to the result of the test command, it is advisable to use the jump command jnz label (Jump if Not Zero) - jump if the zero flag zf is non-zero, or a command with the opposite action - jz label (Jump if Zero) - jump if the zero flag zf = 0.

The next two commands search for the first bit of the operand set to 1. You can search from the beginning or the end of the operand:

1) bsf operand_1, operand_2 (Bit Scanning Forward) – scanning bits forward. The instruction scans the bits of operand_2 from least significant to most significant (from bit 0 to most significant bit) looking for the first bit set to 1. If one is found, the number of this bit is entered into operand_1 as an integer value. If all bits of operand_2 are 0, then the zero flag zf is set to 1, otherwise the zf flag is reset to 0;

2) bsr operand_1, operand_2 (Bit Scanning Reset) – scanning bits in reverse order. The instruction looks (scans) the bits of operand_2 from most significant to least significant (from most significant bit to bit 0) looking for the first bit set to 1. If one is found, the number of this bit is entered into operand_1 as an integer value. It is important that the position of the first one bit on the left is still counted relative to bit 0. If all bits of operand_2 are equal to 0, then the zero flag zf is set to 1, otherwise the zf flag is reset to 0.

In the latest models of Intel microprocessors, several more commands have appeared in the group of logical commands that allow access to one specific bit of the operand. The operand can be located either in memory or in a general-purpose register. The bit position is specified by the offset of the bit relative to the least significant bit of the operand. The offset value can be specified either as a direct value or contained in a general-purpose register. You can use the results of the bsr and bsf commands as the offset value. All instructions assign the value of the selected bit to the CE flag

1) bt operand, bit offset (Bit Test) – check the bit. The command transfers the bit value to the cf flag;

2) bts operand, bit offset (Bit Test and Set) – checking and setting the bit. The instruction transfers the bit value to the CF flag and then sets the bit to be tested to 1;

3) btr operational, bit offset (Bit Test and Reset) – checking and resetting the bit. The instruction transfers the value of a bit to the CF flag and then sets this bit to 0;

4) btc operand, bit offset (Bit Test and Convert) – check and invert the bit. The instruction transfers the value of a bit to the cf flag and then inverts the value of that bit.

Shift Commands

The instructions in this group also provide manipulation of individual bits of the operands, but in a different way than the logical instructions discussed above.

All shift instructions move bits in the operand field to the left or right depending on the opcode. All shift instructions have the same structure - cop operand, shift_counter.

Number of shifted bits – shift_counter – is located in the place of the second operand and can be specified in two ways:

1) statically, which involves specifying a fixed value using an immediate operand;

2) dynamically, which means storing the shift counter value in the cl register before executing the shift instruction.

Based on the size of the cl register, it is clear that the value of the shift counter can range from 0 to 255. But in fact, this is not entirely true. For optimization purposes, the microprocessor only accepts the value five least significant bits counter, i.e. the value ranges from 0 to 31.

All shift commands set the carry flag cf.

As bits are shifted beyond the operand, they first hit the carry flag, setting it equal to the value of the next bit that ends up outside the operand. Where this bit goes next depends on the type of shift instruction and the program algorithm.

Based on the operating principle, shift commands can be divided into two types:

1) linear shift commands;

2) cyclic shift commands.

Linear shift commands

Commands of this type include commands that perform a shift according to the following algorithm:

1) the next “pushed” bit sets the CF flag;

2) the bit introduced into the operand from the other end has the value 0;

3) when the next bit is shifted, it goes into the CF flag, and the value of the previous shifted bit is lost! Linear shift commands are divided into two subtypes:

1) logical linear shift commands;

2) arithmetic linear shift commands.

Logical linear shift commands include the following:

1) shl operand, shift_counter (Shift Logical Left) – logical shift to the left. The contents of the operand are shifted left by the number of bits determined by the shift_count value. On the right (in the position of the least significant bit) zeros are entered;

2) shr operand, shift_counter (Shift Logical Right) – logical shift to the right. The contents of the operand are shifted to the right by the number of bits determined by the shift_count value. On the left (in the position of the most significant, sign bit) zeros are entered.

Figure 30 shows how these commands work.

Rice. 30. Scheme of operation of linear logical shift commands

Arithmetic linear shift instructions differ from logical shift instructions in that they operate in a special way on the sign bit of the operand.

1) sal operand, shift_counter (Shift Arithmetic Left) – arithmetic shift to the left. The contents of the operand are shifted left by the number of bits determined by the shift_count value. To the right (in the position of the least significant bit) are zeros. The sal command does not preserve sign, but sets flag with/in case of sign change another retractable bit. Otherwise, the sal command is completely similar to the shl command;

2) sar operand, shift_counter (Shift Arithmetic Right) – arithmetic shift to the right. The contents of the operand are shifted to the right by the number of bits determined by the value shift_counter. On the left, zeros are entered into the operand. The sar command preserves the sign, restoring it after shifting each next bit.

Figure 31 shows how linear arithmetic shift instructions work.

Rice. 31. Scheme of operation of linear arithmetic shift commands

Rotate Commands

Rotate shift commands are commands that store the values ​​of the bits being shifted. There are two types of rotation commands:

1) simple cyclic shift commands;

2) cyclic shift commands via the carry flag cf.

To the teams simple cyclic shifts include:

1) rol operand, shift_counter (Rotate Left) – cyclic shift to the left. The contents of the operand are shifted left by the number of bits determined by the operand shift_counter. Left-shifted bits are written to the same operand on the right;

2) gog operand, shift_counter (Rotate Right) – cyclic shift to the right. The contents of the operand are shifted to the right by the number of bits determined by the operand shift_counter. Right-shifted bits are written to the same operand on the left.

Rice. 32. Scheme of operation of simple cyclic shift commands

As can be seen from Figure 32, simple cyclic shift instructions perform one useful action during their operation, namely: the cyclically shifted bit is not only pushed into the operand from the other end, but at the same time its value becomes the value of the CE flag

Rotate Commands via carry flag CF differ from simple cyclic shift commands in that the bit being shifted does not immediately go to the operand from its other end, but is first written to the carry flag CE Only the next execution of this shift instruction (assuming it is executed in a loop) results in the previously shifted bit being placed at the other end of the operand(Fig. 33).

To cyclic shift commands via carry flag the following are related:

1) rcl operand, shift_counter (Rotate through Carry Left) – cyclic shift to the left through carry.

The contents of the operand are shifted left by the number of bits determined by the operand shift_counter. The shifted bits alternately become the value of the carry flag cf.

2) rcg operand, shift_counter (Rotate through Carry Right) – cyclic shift to the right through carry.

The contents of the operand are shifted to the right by the number of bits determined by the operand shift_counter. The shifted bits alternately become the value of the carry flag CF.

Rice. 33. Cyclic shift commands via carry flag CF

From Figure 33 it is clear that when shifting through the carry flag, an intermediate element appears, with the help of which, in particular, it is possible to replace cyclically shifted bits, in particular, mismatch bit sequences.

By mismatching a bit sequence hereinafter we mean an action that allows us to in some way localize and extract the necessary sections of this sequence and write them to another location.

Additional shift commands

The command system of the latest Intel microprocessor models, starting with the i80386, contains additional shift commands that expand the capabilities we discussed earlier. These are shift commands double precision: 1) shld operand_1, operand_2, shift_counter – double precision left shift. The shld command performs a replacement by shifting the bits of operand_1 to the left, filling its bits on the right with the values ​​of the bits displaced from operand_2 according to the diagram in Fig. 34. The number of bits to be shifted is determined by the value shift_counter, operand_2 does not change.

Rice. 34. Scheme of the shld command

2) shrd operand_1, operand_2, shift_counter – double precision right shift. The instruction performs the replacement by shifting the bits of operand_1 to the right, filling its bits on the left with the values ​​of the bits displaced from operand_2 according to the diagram in Figure 35. The number of bits shifted is determined by the value shift_counter, which can be in the range 0... 31. This value can be specified as an immediate operand or contained in the cl register. Meaning operand_2 does not change.

Rice. 35. Scheme of the shrd command

As we noted, the shld and shrd commands perform shifts of up to 32 bits, but due to the peculiarities of specifying the operands and the operating algorithm, these commands can be used to work with fields up to 64 bits in length.

2. Control Transfer Commands

We met some of the teams that make up linear sections of the program. Each of them generally performs some actions to convert or transfer data, after which the microprocessor transfers control to the next command. But very few programs work in such a consistent manner. There are usually points in a program at which a decision must be made about which command will be executed next. This solution could be:

1) unconditional - at this point it is necessary to transfer control not to the next command, but to another, which is located at some distance from the current command;

2) conditional – the decision about which command will be executed next is made based on the analysis of some conditions or data.

A program is a sequence of commands and data that occupy a certain amount of RAM space. This memory space can be either contiguous or made up of multiple fragments.

The microprocessor knows which program instruction should be executed next by the contents of a pair of registers cs:(e)ip:

1) cs – segment code register, which contains the physical (base) address of the current code segment;

2) eip/ip – instruction pointer register, which contains a value representing the memory offset of the next instruction to be executed relative to the beginning of the current code segment.

Which specific register will be used depends on whether the addressing mode is set to use16 or use32. If use 16 is specified, then ip is used, if use32, then eip is used.

Thus, control transfer instructions change the contents of the cs and eip/ip registers, as a result of which the microprocessor selects for execution not the next program command in order, but a command in some other section of the program. The conveyor inside the microprocessor is reset.

Based on the principle of operation, microprocessor commands that ensure the organization of transitions in the program can be divided into 3 groups:

1. Commands for unconditional transfer of control:

1) unconditional jump command;

2) command to call a procedure and return from a procedure;

3) command to call software interrupts and return from software interrupts.

2. Conditional transfer of control commands:

1) jump commands based on the result of the page comparison command;

2) transition commands based on the state of a certain flag;

3) commands to navigate through the contents of the ecx/cx register.

3. Cycle control commands:

1) command for organizing a cycle with a counter ecx/cx;

2) a command to organize a cycle with an ecx/cx counter with the possibility of early exit from the cycle under an additional condition.

Unconditional jumps

The previous discussion has revealed some details of the transition mechanism. Jump instructions modify the eip/ip instruction pointer register and possibly the cs code segment register. What exactly needs to be modified depends on:

1) on the type of operand in the unconditional jump command (near or far);

2) from the indication before the jump address (in the jump command) modifier; in this case, the jump address itself can be located either directly in the command (direct jump), or in a register or memory cell (indirect jump).

Modifier can take the following values:

1) near ptr – direct transition to a label within the current code segment. Only the eip/ip register is modified (depending on the specified type of code segment use16 or use32) based on the address (label) specified in the command or an expression using the value extraction character - $;

2) far ptr – direct transition to a label in another code segment. The jump address is specified as an immediate operand or address (label) and consists of a 16-bit selector and a 16/32-bit offset, which are loaded into the cs and ip/eip registers, respectively;

3) word ptr – indirect transition to a label within the current code segment. Only eip/ip is modified (by the offset value from memory at the address specified in the command, or from the register). Offset size 16 or 32 bits;

4) dword ptr – indirect transition to a label in another code segment. Both registers – cs and eip/ip – are modified (by a value from memory - and only from memory, from a register). The first word/dword of this address represents the offset and is loaded into ip/eip; the second/third word is loaded into cs. jmp unconditional jump command

The syntax of the unconditional jump command is jmp [modifier] jump_address - an unconditional jump without storing information about the return point.

The jump_address is either a label address or the address of the memory area where the jump pointer is located.

In total, the microprocessor instruction system contains several jmp unconditional jump machine instruction codes.

Their differences are determined by the transition distance and the method of specifying the target address. Range transition is determined by the location of the operand transition_address. This address may be in the current code segment or in some other segment. In the first case, the transition is called intrasegmental, or loved ones, in the second – intersegmental, or distant An intra-segment jump assumes that only the contents of the eip/ip register are changed.

There are three options for intra-segment use of the jmp command:

1) straight short;

2) straight;

3) indirect.

Procedures

Assembly language has several tools that solve the problem of duplicating sections of program code. These include:

1) mechanism of procedures;

2) macro assembler;

3) interrupt mechanism.

The procedure, often called subroutine - this is the basic functional unit of decomposition (division into several parts) of some task. A procedure is a group of commands for solving a specific subtask and has the means of obtaining control from the point of calling a higher-level task and returning control to this point.

In the simplest case, a program may consist of one procedure. In other words, a procedure can be defined as a correctly formatted set of commands, which, once described, can be called, if necessary, anywhere in the program.

To describe a sequence of commands as a procedure, assembly language uses two directives: PROC and ENDP.

The syntax for describing the procedure is as follows (Fig. 36).

Rice. 36. Syntax for describing a procedure in a program

From Figure 36 it can be seen that in the procedure header (PROC directive) only the procedure name is required. Among the large number of operands of the PROC directive, [distance] deserves special mention. This attribute can take values ​​near or far and characterizes the possibility of calling a procedure from another code segment. By default, the [distance] attribute is set to near.

The procedure can be placed anywhere in the program, but in such a way that control does not accidentally fall on it. If a procedure is simply inserted into the general command stream, then the microprocessor will perceive the procedure commands as part of this flow and, accordingly, will execute the procedure commands.

Conditional jumps

The microprocessor has 18 conditional jump instructions. These commands allow you to check:

1) the relationship between signed operands (“more – less”);

2) the relationship between unsigned operands (“above – below”);

3) states of arithmetic flags ZF, SF, CF, OF, PF (but not AF).

The conditional jump commands have the same syntax:

jcc transition_label

As you can see, the mnemonic code of all commands begins with “j” - from the word jump(bounce), her - defines the specific condition analyzed by the command.

Regarding the operand transition_label, then this label can only be located within the current code segment; intersegment transfer of control in conditional transitions is not allowed. In this regard, the question of the modifier, which was present in the syntax of the unconditional jump commands, disappears. In early microprocessor models (i8086, i80186 and i80286), conditional jump instructions could only make short jumps - a distance of -128 to +127 bytes from the instruction following the conditional jump instruction. Starting with the 80386 microprocessor model, this limitation is removed, but, as you can see, only within the current code segment.

In order to make a decision about where control will be transferred with a conditional jump command, a condition must first be generated on the basis of which the decision to transfer control will be made.

The sources of such a condition may be:

1) any command that changes the state of arithmetic flags;

2) the compare command page, which compares the values ​​of two operands;

3) state of the ecx/cx register.

cmp compare command

The compare page command has an interesting operating principle. It is absolutely the same as the subtraction command - sub operand, operand_2.

The page command, like the sub command, subtracts operands and sets flags. The only thing it does not do is write the result of the subtraction in place of the first operand.

The syntax of the page command is page operand_1, operand_2 (compare) – compares two operands and sets flags based on the comparison results.

Flags set by the page command can be analyzed using special conditional branch commands. Before we look at them, let's pay a little attention to the mnemonics of these conditional jump commands (Table 16). Understanding the notation when forming the names of conditional jump commands (the element in the name of the jcc command, designated by us) will make it easier to memorize them and further practical use.

Table 16. Meaning of abbreviations in the jcc command name
Table 17. List of conditional jump commands for command page operand_1, operand_2

Do not be surprised by the fact that the same flag values ​​correspond to several different mnemonic codes of conditional jump commands (they are separated from each other by a slash in Table 17). The difference in name is due to the desire of microprocessor designers to make it easier to use conditional jump instructions in combination with certain groups of instructions. Therefore, different names rather reflect different functional orientations. However, the fact that these commands respond to the same flags makes them absolutely equivalent and equal in the program. Therefore, in Table 17 they are grouped not by name, but by the flag values ​​(conditions) to which they react.

Conditional Branch Instructions and Flags

The mnemonic notation for some conditional jump commands reflects the name of the flag they operate on, and has the following structure: the character "j" comes first. (Jump, transition), the second is either the flag designation or the negation symbol “n”, followed by the name of the flag. This team structure reflects its purpose. If there is no “n” character, then the state of the flag is checked; if it is equal to 1, a transition is made to the jump label. If the character “n” is present, then the state of the flag is checked for equality 0, and if successful, a jump is made to the jump label.

Command mnemonic codes, flag names and transition conditions are given in Table 18. These commands can be used after any commands that change the specified flags.

Table 18. Conditional jump commands and flags

If you look closely at Tables 17 and 18, you can see that many of the conditional jump commands in them are equivalent, since both are based on the analysis of the same flags.

Conditional jump instructions and the ecx/cx register

The architecture of the microprocessor involves the specific use of many registers. For example, the EAX/AX/AL register is used as an accumulator, and the BP and SP registers are used to work with the stack. The ESH/CX register also has a specific functional purpose: it performs the role counter in loop control commands and when working with character strings. It is possible that functionally the conditional jump command associated with the ecx/cx register would be more correctly classified as this group of commands.

The syntax for this conditional branch command is:

1) jcxz jump_label (Jump if ex is Zero) – jump if cx is zero;

2) jecxz jump_label (Jump Equal exx Zero) – jump if exx is zero.

These commands are very convenient to use when organizing a loop and when working with strings of characters.

It should be noted that there is a limitation inherent to the jcxz/jecxz command. Unlike other conditional control transfer instructions, the jcxz/jecxz instruction can only address short jumps - at -128 bytes or +127 bytes from the next instruction.

Organizing cycles

The cycle, as you know, is an important algorithmic structure, without the use of which, probably, not a single program can do. You can organize cyclic execution of a certain section of the program, for example, using conditional transfer commands or the unconditional jump command jmp. With this type of cycle organization, all operations related to its organization are performed manually. But, given the importance of such an algorithmic element as a cycle, the microprocessor developers introduced a group of three commands into the command system to facilitate the programming of cycles. These commands also use the ecx/cx register as cycle counter.

Let's give a brief description of these commands: 1) loop jump_label (Loop) – repeat the cycle. The command allows you to organize loops similar to for loops in high-level languages ​​with automatic decrement of the loop counter. The team's job is to do the following:

b) comparing the ESX/CX register with zero: if (ECX/CX) = 0, then control is transferred to the next command after the loop;

2) loope/loopz transition_label

The loope and loopz commands are absolute synonyms. The work of the commands is to perform the following actions:

a) decrement of the ESH/CX register;

c) analysis of the state of the zero flag ZF if (ECX/CX) = 0 or XF = 0, control is transferred to the next command after the loop.

3) loopne/loopnz transition_label

The loopne and loopnz commands are also absolute synonyms. The work of the commands is to perform the following actions:

a) decrement of the ESH/CX register;

b) comparing the ESX/CX register with zero;

c) analysis of the state of the zero flag ZF: if (ECX/CX) = 0 or ZF = 1, control is transferred to the next command after the loop.

The loope/loopz and loopne/loopnz commands are inverse in their operating principle. They extend the action of the loop command by additionally analyzing the zf flag, which makes it possible to organize an early exit from the loop, using this flag as an indicator.

The disadvantage of the loop, loope/loopz and loopne/loopnz commands is that they only implement short jumps (from -128 to +127 bytes). To work with long loops, you will need to use conditional branch commands and the jmp command, so try to master both methods of organizing loops.

Basics of programming MP devices (Lecture)

LECTURE PLAN

1. Classification of microprocessor commands

2.Types of addressing

3. Structure and command formats of MP KR580VM80

1. Classification of microprocessor commands

As already noted, the fundamental advantage of MP is programmability. This means that by applying commands to the MP input, it is possible to ensure the desired sequence of operations, i.e. implementation of a specific algorithm. The algorithm of the problem being solved can be as complex as desired, it is only necessary that this algorithm be broken down into steps in accordance with the command system of the MP. Therefore, the command system is important not only from the point of view of what the MP can do, but also how the algorithm is executed. The presence or absence of any command or group of commands can significantly affect the choice of MP for a particular application.

The classification of MP commands is presented in Figure 8.

Based on the number of memory cells required to accommodate one command, commands of one, two or three words in length are distinguished. Instructions that are two or three words long require two or three memory access cycles, respectively, to fetch.

In many cases, in particular when comparing MPs with similar architectures, it is useful to classify commands in accordance with the architectural characteristics of the MP.

From a functional point of view, teams are divided into three large groups: transmission, management and data processing. Let us consider in detail the main commands used in MP, using the classification according to functional characteristics. The names of the commands will be denoted by Russian words indicating the meaning of the operations being performed.

Data transfer commands provide simple transfer of information without performing any processing operations. The commands in this group are divided into commands related to memory access, register access commands, and input/output commands.

Commands related to memory access include:

REMEMBER(WRITE), by which the contents of the register are sent to the memory cell.

Commands related to transferring a byte or word must indicate the number of a specific register, the address of the memory cell and, if necessary, the number of the storage module.

Commands associated with accessing registers must indicate the number of the source of information and the number of the result register. This subgroup of data transfer commands includes the commands:

DOWNLOAD DIRECTLY, in which the constant specified in the command code is written to the register;

FORWARD, through which the contents of one register are sent to another.

I/O commands include:

ENTER, by which the contents of the input device are sent to the internal register of the MP;

CONCLUSION, in which the contents of the internal register of the MP (usually an accumulator) are sent to the output device.

Control commands , often called transition commands, allow you to perform various actions in accordance with the value of external signals or conditions generated within the system. All control commands are divided into unconditional and conditional transition commands.

Unconditional jump commands include:

UNCONDITIONAL JUMP(BP), according to which the contents of the address field of the BP command are written to the program counter, i.e. provides a transition in the program to the address specified in the command;

UNCONDITIONAL TRANSFER WITH REFUND(transition to a subroutine), according to which new contents are written to the program counter (the address of the first command of the subroutine), but unlike the BP command, the state of the program counter and some other registers is saved in memory. When a subroutine is executed on its last RETURN command, the contents of the program counter and all registers are restored.

Conditional jump instructions check the state of a register bit, flag flip-flop, or other parameter. The result of the check determines whether the transition will be performed or not. Typically, the transition is carried out if the result of the check matches the condition specified in the command. This subgroup of control commands includes:

CONDITIONAL JUMP(UP) by address. The code of the UP command must indicate the condition being checked, for which the MT uses a zero or non-zero value of the result, a positive or negative sign of the result, the presence or absence of carry signals, overflow, etc. When the condition is met, the contents of the address counter are written to the program counter. UE command fields, i.e. provides a transition in the program to the address specified in the command. If the condition is not met, control is transferred to the next program command;

CONDITIONAL TRANSITION WITH RETURN, which differs from the UNCONDITIONAL JUMP WITH RETURN command in that the transition to the subroutine occurs only when the specified condition is met.

Typically, the MP command system includes several more auxiliary commands that allow you to control the state of registers or triggers that affect the execution of conditional transitions, for example: SET FLAG, RESET FLAG, SET BATTERY HIGH BIT, RESET BATTERY HIGH BIT, etc.

Data Processing Commands are divided into arithmetic and logical. Arithmetic ones include:

FOLD the contents of two registers or a register and a memory cell;

SUBTRACT from the contents of a memory cell or register; contents of a register;

INCREASE BY 1(INCREMENT) contents of a memory cell or register (stack pointer, index register, accumulator);

DECREASE BY 1(DECREMENT) contents of a memory cell or register;

ADD WITH CARRY OUT, by which addition is performed taking into account the state of the transfer trigger. This makes it easy to organize the processing of large numbers;

SUBTRACT ACCOUNTING THE LOAN;

SHIFT contents of a memory cell or register (usually one bit).

The subgroup of logical commands includes the following commands:

AND(LOGICAL MULTIPLY), by which the conjunction operation is performed between the contents of two registers or a memory cell and a register;

OR(LOGICAL ADDITION), by which a disjunction operation is performed between the contents of two registers or a memory cell and a register;

INVALIDITY, which performs a bitwise comparison of the contents of two registers or a memory cell and a register;

INVERSION contents of a memory cell or register.

2.Types of addressing

One of the most important architectural characteristics of MP is the list of possible methods of accessing memory or types of addressing. The addressing capabilities of MP are significant from two points of view.

First, a large amount of memory requires a large address length, since an n-bit address allows access to memory with a capacity of 2n words. Typical 8-bit MP words make it possible to directly access only 256 memory cells, which is clearly not enough. If we take into account that accessing memory is the most common operation, then it is obvious that the efficiency of using MP is largely determined by the methods of addressing a large volume of memory with a small bit capacity of MP.

Secondly, for ease of programming, it is desirable to have a simple system for generating data addresses when working with arrays, tables and pointers. Let's look at ways to solve these problems.

If the address field of the command is limited and insufficient to directly access any memory cell, then the memory in such cases is divided into pages, where 2n memory cells are considered a page.

To match the address field of a small-bit command with large-capacity memory (to solve the “page” problem), various types of addressing are used in the MP:

Direct addressing to the current page . With this addressing, the program counter is divided into two fields; the high-order bits indicate the page number, and the low-order bits indicate the address of the cell on the page. The address field of the command contains the address of the cell on the page, and the page address must be set in some other way, for example, using a special command.

Direct addressing using page register. The MP must have a programmatically accessible page register loaded by a special command. This register adds several bits to the address field of the instruction, necessary for addressing all memory.

Direct addressing using double words. To increase the length of the address field of a command, an additional word is allocated for the address (and if necessary, two).

Addressing relative to the program counter. The instruction address field is treated as a signed integer, which is added to the contents of the program counter to form the execution address. This relative addressing method creates a floating page and makes it easier to move programs around in memory.

Addressing relative to index register. The execution address is formed by summing the contents of the index register and the address field of the command, considered as a signed integer. The index register is loaded with special commands.

Indirect addressing . When indirect addressing is used, the address field of the command specifies the address on the current page where the executive address is stored. In this case, an additional bit is required in the command field - a sign of indirect addressing. The executive address can be stored not in a memory cell, but in a general-purpose register. In this case, indirect addressing is called register addressing.

3. Structure and command formats of MP KR580VM80

The MP command system of the KR580VM80 series contains commands in three formats: single-byte, double-byte and three-byte.

The contents of the first byte indicate the command format, operation code, type of addressing, and registers or register pairs, if they are involved in the operation. However, it is impossible to specify the specific bits that are allocated to the first three of the specified components of the command, because they can be located in any bits of the command. But despite this, we will assume that they are encoded as one field, which is called the operation code field. Variants of formats for the first byte of the command are shown in Figure 9.

If registers are involved in the operation, one or two of them may be specified in the first byte of the command. In this case, quite specific bits are assigned to the register numbers in the command field: the three low-order bits (b2 – b0) encode the number of the source register containing the operand, and the three middle ones (b5 – b3) – the number of the destination register into which the result of the operation is sent. In those cases, when both or one of these registers are not involved in the execution of the operation, the corresponding bits are used for the operation code.

The following register encoding is accepted:

000 – register B, 100 – register H,

001 – register C, 101 – register L,

010 – register D, 110 – memory cell,

011 – register E, 111 – battery A.

Code 100 is a sign of indirect memory addressing using a 16-bit address located in the H and L registers. Depending on the location of this code in the command, the corresponding memory cell is accessed either for an operand or for writing the results of the operation.

A number of MP commands provide for the processing or transmission of double-length numbers. In these cases, pairs of registers B and C, D and E, or H and L are combined into 16-bit registers numbered 00, 01 and 10, respectively. The numbers of register pairs in commands are assigned to the bits b2 and b1 (source register), b5 and b4 (destination register), and the bits b0 and b3 are used to indicate the operation code.

Double-byte commands in the MP include commands with direct addressing and input/output commands. Accordingly, the second byte of the command of this group contains an 8-bit operand or an 8-bit address of an input or output device.

In three-byte instructions, the second and third bytes contain 16-bit addresses (in direct-addressing instructions) or 16-bit operands (in instructions for loading register pairs and stack pointer).

After each ALU operation is executed, five signs are generated, the values ​​of which can influence the execution of subsequent information processing and conditional control transfer commands. However, it should be borne in mind that different commands have different effects on individual signs.

For the convenience of saving and restoring the state of the MP during interruptions and transitions to subroutines, all of the specified characteristics are stored in a special register - the characteristics register. The location of signs in the register bits is shown in the table.

where S is the “sign” attribute (takes the value of the most significant bit

result);

Z – sign of zero result;

AC is a sign of auxiliary transfer (if there is transfer

between byte tetrads, then AC=1, otherwise AC=0;

P – a sign of parity of the result (if the number of ones in the byte

result is even, then P=1, otherwise P=0);

C – a sign of transfer or loan (if, when executing commands,

When there was a transfer from a senior rank or a loan to a senior-

The highest digit is C=1, otherwise C=0).

Note: For logical multiplication commands, the auxiliary carry sign AC takes the value of the fourth bit of the result.

The complete command system of the MP series KR580VM80 is given in the appendix of the textbook “Microprocessors and microprocessor systems”. There, for each command, it is indicated how, after its execution, the value of each attribute changes: it is set in accordance with the result of the operation (+), does not change (–), is reset to zero (0) or set to one (1).

In general, the command should contain the following information:

–operation code indicating the operation that the MP must perform;

–addresses of two operands (addends, subtrahends, etc.). If any of the operands is a constant, then instead of its address, the value of the operand itself can be specified in the command. However, this circumstance must be reflected in the operation code so that the MP uses the appropriate part of the command for its intended purpose;

–address of the memory cell into which the result of the operation should be placed;

–address of the next command.

Those. the command is generally four-address. However, this command structure leads to a longer command format, which, in turn, is associated with a more complex processing process and processor structure. Therefore, in MP technology, addressless and unicast commands are most widespread, making it possible to build a simple processor. However, when performing complex operations, various command formats are used.

The 580 series MP instruction system has single-byte, double-byte and three-byte instructions.

Information about how the command to be addressed is contained in the opcode of the first byte of the command.

To speed up calculations, some operands are stored in the RON block. Instructions that operate on these operands use shortened address codes (register addressing).

These commands allow you to eliminate the relatively long cycle of accessing RAM and thereby significantly increase the speed of operations. Due to the limited capacity of the RON and when working with a large array of data, other addressing methods are used that allow access to operands located in memory external to the MP. The most common is register indirect addressing, which uses an HL register pair.

In the group of control transfer commands, there are four types of commands: unconditional branches, conditional branches, loops and interrupts .

Unconditional jump commands. Includes three mnemonic codes: JMP (unconditional jump), CALL (subroutine call) and RET (return from subroutine).

The JMP command allows you to jump to any point in the program, located both in the current program segment and in another segment. When jumping within the current program segment, the first three JMP instruction formats are used.

The first format provides a transition to an arbitrary point in the program within the current program segment, for which a 16-bit offset is added to the IP content in two's complement code, the most significant bit of which is signed. The second, shortened format allows you to jump to a point in the program no more than -128-f-127 addresses from the JMP instruction. Finally, the third format loads the instruction pointer with a 16-bit number, which is located at the executive address EA, determined by the postbyte. This transition is called indirect because indirect addressing is used.

To implement an unconditional jump to a program point located outside the current program segment when a reload of the CS segment register is required, the fourth and fifth JMP instruction formats are used.

The fourth format defines a direct intersegment transition, in which the second and third bytes of the format indicate the relative address of the transition point, and the fourth and fifth bytes indicate the new CS value. The fifth format, using a postbyte, allows you to determine the executive address EA, at which the relative address of the transition point is located (in memory bytes with addresses EA, EA+1), and the new CS value (in memory bytes EA+2, EA+3).

The CALL command allows you to call a subroutine located either in the current program segment or in another memory area. It has the same formats as the JMP command, except it is shorter. Unlike the JMP command of a similar format, the CALL command, before changing the IP or IP and CS values, automatically writes the current values ​​of these registers to the stack, which ensures that the return point from the subroutine is remembered.

To return from a subroutine, use the RET command, which transfers control to the return address pushed onto the stack when executing the previous CALL command. When returning from subroutines located in the current program segment, the first two formats of the RET instruction are used, and the second format differs from the first in that a constant written in the 2nd and 3rd bytes of the instruction is added to the contents of the stack pointer. This allows, simultaneously with return from the subroutine, to reset the parameters written to the stack during execution of this subroutine and not used in the future.

For intersegment return, the third and fourth RET formats are used, which provide recovery of the contents of both the instruction pointer and the program segment.

Conditional jump commands. Transfer control depending on the results of previous operations. There are three types of conditional jumps that are used to establish relationships between signed numbers, unsigned numbers, and arbitrary numbers. In the first two varieties, different command mnemonic codes are selected for the same relationships between numbers, since different flag values ​​correspond to the same relationships between signed and unsigned numbers.

In the mnemonic codes of conditional jump commands, when comparing signed numbers, the letter is used to indicate the “greater than” condition G (Greater- more), and to designate - “less” letter L (Less- less). For similar conditions, when comparing unsigned numbers, letters are used respectively A (Above- above) and Below- under). The equality condition is denoted by the letter E (Equal- is equal), and failure to fulfill some condition - by the letter N(Not- Not). It should be noted that it is allowed to use two different mnemonic codes for each command; for example, the mnemonic codes JL and JNGF are equivalent, since the conditions “less than” and “not greater than or equal to” are identical.

A complete list of command mnemonic codes, conditions being checked, as well as the corresponding Boolean combinations of flags and their values ​​are given in Table. 1.4.

Table 1.4

Command mnemonic code	Condition	Meaning of the flags
	For signed numbers
JL/JNGE	Less/not more than or equal to	SF + OF = l
JNL/JGE	Not less than/greater than or equal to	SF + OF = 0
JG/JNLE	More than/not less than or equal to	(SF + OF) V ZF = 0
JNG/JLE	Not greater than/less than or equal to For unsigned numbers	(SF + OF) V ZF = l
JB/JNAE	Less/not more than or equal to	CF=1
JNB/JAE	Not less than/greater than or equal to	CF=0
JA/JNBE	More	CF V ZF = 0
JNA/JBE	No more For other data	CF V ZF = 1
JE/JZ	Equal/zero	ZF = 1
JNE/JNZ	Not equal/zero	ZF = 0
JS	By minus	SF = 1
JNS	On the plus side	SF = 0
JO	Overflow	OF = l
JNO	By absence of overflow	OF = 0
JP/JPE	By even parity	PF = 1
JNP/JPO	By odd parity	PF = 0

All conditional jump instructions have the same two-byte format, the first byte of which is the operation code (OPC), and the second is an 8-bit offset, which is treated as a signed number and therefore allows address changes in the range from -128 to + 127. If a more distant (“far”) transition is required when a condition is met, an additional unconditional transition command is used.

The execution time of each of the conditional jump instructions is indicated for two cases: 1) the condition is satisfied and control is actually transferred in accordance with the offset, 2) the condition is not satisfied, so control is transferred to the next instruction.

Teams for organizing cycles. Introduced into the CPU for the convenience of performing computational cycles. These include the following mnemonic codes: LOOP (loop until (CX) is not equal to 0), LOOPNZ/LOOPNE (loop until zero/not equal to), LOOPZ/LOOPE (loop until zero/equal to) and JCXZ (jump on zero in SH). Each of these commands has a two-byte format, the second byte of which specifies the 8-bit offset used to arrange the jump. This offset is treated as a signed number and is signed-extended to 16 bits before the jump address is calculated.

Using loop commands together with commands for manipulating string elements, you can create fairly complex string conversion programs. Let's consider an example of composing a program to convert a string of data written in the hexadecimal number system into some code for which the conversion table is located in memory from the starting address specified in BX, as required to use the table conversion command for XLAT codes. Let us further assume that the source string contains 80 elements and is located in memory from the relative starting address 100, and the result string should be placed from the relative address 200. The program that converts the source string into the result string, with the value of the direction flag DF=0, will have the form :

MOVSI ,100
MOV DI ,200
MOV CX, 80

The XLAT table conversion command described in 1.2 is used here.

Interrupt commands. Includes three mnemonics: INT (interrupt), INTO (interrupt on overflow), and IRET (interrupt return).

Interrupt command INT at v=1 has a two-byte format, the second byte of which contains an 8-bit number defining the type (type) or interrupt level. By INT command type The processor proceeds to execute the interrupt service program of the specified level, and the actions necessary to ensure a return to the interrupt point are automatically performed. These actions are as follows: the contents of the F flags register are written to the stack (PUSHF), the IF and TF flags are reset, the current values ​​of the CS register and the IP instruction pointer are written to the stack.

To determine the starting address of the service program according to the value type The interrupt level table is used. For each of the 256 interrupt levels in this table, four bytes are allocated: the first two bytes determine the value of the IP instruction pointer, the second - the value of the CS segment register. This four bytes determines the starting addresses of service programs (pairs of CS, IP values), which must first be written to memory cells at absolute addresses 0-3FFH. Table address corresponding to that specified in the INT command type interrupt level is determined in the CPU as follows. After storing the current values ​​of CS and GR in the stack, loading is carried out: CS = type x 4 + 2 and IP = type x 4. New CS and IP values ​​taken from address cells respectively type x 4 + 2 And type x 4, determine the starting address of the required maintenance program.

The INT interrupt command discussed above when the field value is v=0 has a single-byte format, i.e. it does not require special indication of the interrupt level. This command is automatically perceived by the processor as a level 3 interrupt. (type=3) and is commonly used in programs as a checkpoint.

The INTO overflow interrupt command causes a transition to servicing the fourth level interrupt (type = 4) in the case when the value of the overflow flag OF = 1. The INTO command is typically used after signed arithmetic commands. Typically, the first few interrupt levels (up to 32) are reserved for processing a number of specific situations, such as an attempt to divide by zero, overflow, and the like.

A peculiarity of processing interrupts of reserved levels is that the processor proceeds to servicing them regardless of the value of the interrupt enable flag IF.

The one-byte IRET instruction is placed at the end of each interrupt service routine and provides interrupt return. With this command, the processor retrieves the value of the IP instruction pointer and the CS program segment from the stack, and also restores the previous contents of the F flags register (as with the POPF command). If necessary, the contents of the remaining CPU registers corresponding to the interrupted program can be stored on the stack when moving to the service program and then restored when returning from it using stack access instructions.

By indirect address

PCHL – the jump address is stored in the HL register pair. When it is executed (HL) → PC.

Conditional jump commands

Jcon @, where con is a condition mnemonic from the English word condition.

It was previously noted that the state of the bits (flags) of RgP (F) is used as a transition condition. The mnemonics corresponding to these states are presented in Fig. 6.18.

For example: JC 8BFE – when C=1 goes to address 8BFE, when C=0 the next command at the address is executed.

Commands for calling PP and returning

It was previously noted that the return address is automatically stored on the stack, i.e. (PC) ® stack.

Unconditional commands

CALL @ – subroutine call;

RET – return from subroutine.

Conditional commands

Ccon @ – subroutine call;

Rcon – return from subroutine.

The action of the commands is similar to the action of the conditional jump commands, i.e. if the condition is true, then call or return. If not, then the following commands are executed.

Other control commands

RST n, where n = 0.1,...,7 – restart according to interrupt vector n.

When this command is executed, control is transferred to the subroutine servicing this interrupt. During the execution of the RST instruction, the contents of the PC program counter are stored on the stack, and the address of the corresponding interrupt vector is written to the PC.

This address is set as follows. The RST command has the structure 11NN N111, i.e. one byte. The three-bit NNN combination is specified by the value n (n = 0...7). The value 0000 0000 00NN N000 is entered into the PC command counter, which serves as the address of the corresponding interrupt vector.

Thus, by setting a certain value of n, you can generate the address of one of the 8 interrupt vectors. These addresses are located in the zone from 0000H to 0038H of the address space and go through 8 bytes, i.e. The first 64 memory cells are reserved for them (each of the 8 vectors is allocated 8 bytes). In these zones (8 bytes each) only commands for jumping to the corresponding subroutines (handlers), which are located in other memory areas, are written.

Interrupting subroutines (like normal subroutines) must end with the RET command. During the execution of this command, the address of the main program command before which the interrupt occurred is selected from the stack and transferred to the address register PA, and the value increased by 1 is entered into the program counter.

EI – interrupt enable. This command is placed at the beginning of the program section where interruption is enabled. With this command, the interrupt enable trigger in the MP control unit is set to state 1.

DI – interrupt disable. This command is placed at the end of the program section where the interrupt was enabled and resets the trigger to state 0.

NOP is an "empty" command. Skips 4 measures. Only PC changes.

HLT – stop. Causes program execution to stop and enter the stopped state. The MP is disconnected from the external address and data buses (i.e., their buffers go into state Z). The WAIT (waiting) output is set to level 1. This state can be interrupted by MP start signals or by placing it in the interrupt state.

SELF-TEST QUESTIONS

1. What devices are needed to create a simple microcomputer?

2. List 5 options for microcomputer structures.

3. Using an intermediate interface.

4. What does the concept of “PU controller” include?

5. List the characteristics of the I8080 processor.

6. Data registers. Their purpose.

7. Sign registers. What attributes are stored in these registers?

8. Describe the principle of bidirectional data exchange between internal and external SD.

9. What registers can a programmer use?

10. Give a block diagram of a microcomputer based on MP KR580VM80.

11. What cycles does a machine cycle consist of?

12. List the data formats of MP KR580VM80.

13. List the command formats of the MP KR580VM80.

14. What addressing methods are used in the MP KR580VM80?

15. What groups can the MP KR580VM80 teams be divided into?

16. Single-byte transfers. Give examples of commands from this group.

17. Double-byte transfers. Give examples of commands from this group.

18. What battery operations do you know?

19. Operations in RON and memory. What operations do they include?

20. List the control commands.

CONTROL TASKS

1. The answer sheets must indicate the group number, the student’s last name and the number of his option.

2. Question numbers are selected by the student in accordance with his last two digits in the grade book. In Table 6.1, n-1 is the penultimate digit of the number, and n is the last digit. The cells of the table contain the numbers of questions to which a written answer must be given.

Question numbers Table 6.1

a n a n-1
	1,5,9, 13,16	2,6,10,14,17	3,7,11,15,18	4,8,12,13,19	1,9,11,14,20	2,10,12,15,18	3,5,8, 13,17	4,6,7, 14,19	1,8,10,13,17	2,5,7, 14,18
	3,6,8, 15,19	4,7,9, 13,16	1,5,12,14,20	2,6,11,15,16	3,7,10,13,17	4,8,9, 14,18	1,7,12,13,18	2,8,10,14,19	3,5,11,15,20	4,6,9, 13,17
	2,7,9, 13,20	1,8,11,15,19	4,5,10,15,17	3,6,12,14,16	1,5,9, 13,16	2,6,10,14,17	3,7,11,15,18	4,8,12,13,19	1,9,11,14,20	2,10,12,15,18
	3,5,8, 13,17	4,6,7, 14,19	1,8,10,13,17	2,5,7, 14,18	3,6,8, 15,19	4,7,9, 13,16	1,5,12,14,20	2,6,11,15,16	3,7,10,13,17	4,8,9, 14,18
	1,7,12,13,18	2,8,10,14,19	3,5,11,15,20	4,6,9, 13,17	2,7,9, 13,20	1,8,11,15,19	4,5,10,15,17	3,6,12,14,16	1,5,9, 13,16	2,6,10,14,17
	3,7,11,15,18	4,8,12,13,19	1,9,11,14,20	2,10,12,15,18	3,5,8, 13,17	4,6,7, 14,19	1,8,10,13,17	2,5,7, 14,18	3,6,8, 15,19	4,7,9, 13,16
	1,5,12,14,20	2,6,11,15,16	3,7,10,13,17	4,8,9, 14,18	1,7,12,13,18	2,8,10,14,19	3,5,11,15,20	4,6,9, 13,17	2,7,9, 13,20	1,8,11,15,19
	4,5,10,15,17	3,6,12,14,16	1,5,9, 13,16	2,6,10,14,17	3,7,11,15,18	4,8,12,13,19	1,9,11,14,20	2,10,12,15,18	3,5,8, 13,17	4,6,7, 14,19
	1,8,10,13,17	2,5,7, 14,18	3,6,8, 15,19	4,7,9, 13,16	1,5,12,14,20	2,6,11,15,16	3,7,10,13,17	4,8,9, 14,18	1,7,12,13,18	2,8,10,14,19
	3,5,11,15,20	4,6,9, 13,17	2,7,9, 13,20	1,8,11,15,19	4,5,10,15,17	3,6,12,14,16	1,5,9, 13,16	2,6,10,14,17	3,7,11,15,18	4,8,12,13,19

The unconditional transition operation (BP) refers to the operations of unconditional transfer of control and consists of the following. At the beginning of the operation, the contents of the CC, indicating the command that follows the BP (return address), are sent to P1 AU if the program provides for a return; this allows you to save the return address by further transferring the contents of P1 (for example, by the 3G operation) into memory. To do this, the first commands of the program section to which the transition is made must contain a corresponding operation. At the next stage of the operation, the contents of 1-14 bits, which is the transition address, are read from the RAM or ROM cell with the address specified in the BP command in the SchK. At this address, a request is then made to the ROM for the command to which the transition is made.

Shift operation

In the shift format (FSD), the operations “Arithmetic shift right (left)” and “Logical shift right (left)” are encoded. When they are executed, actions are performed on the number located in the AC. The attributes in the command are specified: the direction of the shift (5 r), the types of shifts (8.9 r) and their number (1-4 r). During the operation, the bits of register P2 are shifted, the result is recorded in registers P2 and РСм, and the shift to the right is carried out by 3 bits at the same time, the shift to the left is 1 bit. The value of the 5th bit equal to “1” determines the shift to the left, equal to “0” - to the right.

Operations are cyclical. The number of shift cycles is counted by the cycle counter (CC). Before executing the cyclic part of the operation, the contents of 1-5 bits of the command containing a constant and a shift sign are sent to the center. Next, the contents of P2 are sent to RSM. The shift itself is carried out due to the “oblique” copying of the contents of registers P2 and Pcm into P2’ and Pcm’, respectively. Then the result of the shift from PCm' and P2' through SM1 and SM2 is rewritten into P2 and PSM. The completion of the operation is indicated by the value of SchT =0.

Depending on the type of shift (L or A), either all 16 bits (L) or only 15 bits (mantissa) without a sign (A) are shifted. When A shift to the right, the vacated high-order bits are filled with a sign, and when shifting to the left, the vacated low-order bits are filled with zeros. During a logical shift to the right or left, the vacated bits are filled with zeros.

You can also programmatically change the shift constant.

32 Interaction of nodes and elements of the block diagram of the CB processor when performing conditional jump operations.

Conditional jump operations

The execution of the operation begins with checking the feasibility of the transition condition by comparing the value of the result attribute of the previous operation with the “mask” code in the command. If the condition is met, then the transition to the execution of the command occurs, the address of which is in the address-operand part of the PFU format. If the transition condition is not met, then the command following the “Conditional jump” command in the program is executed.

The “Conditional Jump” (JJ) command occupies two adjacent ROM cells. The first cell contains the command, the second cell contains the jump address. A conditional jump is determined by a combination in the 7-9 bits of the command, the condition for placing the return address is determined by the 6th bit.

When the condition is met, the transition address is entered into the program counter, therefore the code of the next command will be read from the cell with this address. The return address is entered in P1 if the 6th bit is equal to 0 and in Pcm if the value of this bit is equal to one.

If the transition condition is not met, the next instruction is selected from the cell with address code i+2. In this case, the specified code (return address) is entered into P1 regardless of the value of the 6th bit of the command. The latter is determined by the operating algorithm of the SV processor when deciphering the UE operation code.

Entering the return address on the PCM is due to the fact that the output to the code bus from the AC has only the specified register.

A peculiarity of the execution of the NC operation is that if there is code 111 or 000 in the “mask” bits of the command, the conditional transition degenerates into an unconditional one or an operation of sending to the base registers, respectively. In these cases, the jump addresses or the sending address to the base registers are the contents of the address-operand part of the instruction (AOC).

When performing the operation of sending to the BR, the contents of the AOC are sent to one or several BRs at once, depending on the contents of the 15-17 bits of the command. The return address in this case is not sent to P1 and RSM.

Executing a NC operation as a TCU operation can be used in interrupts to jump to interrupting programs. To do this, in the 5th bit of the command, the attribute of a programmed transition (PNT) is set. In this case, the command is read into the processor from ROM via an interrupt signal (ISR). In this case, the ROM access address (interrupt address) is generated by the processor interrupt circuit.

A peculiarity of the operation in this case is that the return address for interrupts is not the address of the command following the command in the FUP format, but the address of the command before which the interrupt occurred. The NPP signal is processed as follows. Based on this signal, the processor's interrupt circuit generates an interrupt address (APr), equal to the address of the first cell of the jump instruction in the FUP(i) format. This address is transferred to memory through the switch and the ROM address register. The interrupt addresses are selected in such a way that the address of the first cell of the command (i) is even, and the address of the second cell (i+1) is odd. The second address is obtained by changing (in hardware) the least significant digit without the participation of the CC from zero to one. In the process of reading a command from the ROM and executing it, the contents of the SchK (K+1) are stored in the register P1 of the AC, and the contents of the second cell of the command (i+1), which is the address of the transition to the command with address j, are entered into the SchK. A request is made to the ROM regarding the new contents of the CC. Thus, the address of the next instruction at the time of interruption (K+1) is stored in register P1. After the interrupt has been processed, this address is used to return to the interrupted program.

33 Interaction of nodes and elements of the block diagram of the SV processor when performing processor and system control operations.